1. Field of the Invention
The present invention relates to the field of crosstalk compensation in connectors and, more particularly, to a technique of maximizing capacitance per unit area while minimizing signal transmission delays in crosstalk compensating printed circuit boards (PCBs).
2. Discussion of the Related Art
Noise or signal interference between conductors in a connector is known as crosstalk. Crosstalk is a common problem in devices using connectors. Particularly, in a system where a modular plug often used with a computer is to mate with a modular jack, the electrical wires (conductors) within the jack and/or plug produce crosstalk.
U.S. Pat. No. 5,997,358 issued to Adriaenssens et al. (hereinafter “the '358 patent”) describes a multi-stage scheme for compensating crosstalk in connectors. The entire contents of the '358 patent are incorporated by reference. Further, the subject matters of U.S. Pat. Nos. 5,915,989; 6,042,427; 6,050,843; and 6,270,381 are also incorporated by reference.
As Illustrated in FIG. 4, the The '358 patent reduces original crosstalk in a modular jack 60 of a connector that receives a plug. The jack 60 includes a PCB 600 with conductors placed on the PCB layers. The original crosstalk between the conductors (Jackwires 61) of the jack 60 is reduced or compensated for by adding a fabricated (compensation) crosstalk at two compensation stages thereby canceling the crosstalk in the plug-jack combination. The compensation crosstalk is created by placing capacitors on the PCB layers and providing crossed-over conductors at different locations (stages) on the PCB layers.
In such crosstalk compensating systems, it is desirable for the crosstalk compensating PCB to have a high dielectric constant (DK) to minimize the PCB space used to achieve the needed capacitive crosstalk compensation. However, the use of a high DK material for the PCB results in long delays in the signal transmission paths of the conductors between the compensation stages which is detrimental to the high frequency performance of the connector.
Therefore, there exits a need for a technique capable of maximizing an efficient PCB space utilization for the capacitive crosstalk compensation while minimizing signal transmission delays in the PCB.